The present application relates generally to clock synthesizers, and more particularly to a clock synthesizer for synthesizing an output clock signal having a frequency near that of a source clock signal.
Clock synthesizers are known for deriving one or more output clock signals from a source clock signal. Such clock synthesizers are employed in various applications including error detection and/or correction schemes used in the transmission of serial data. When performing error detection and/or correction, a serial data transmission system typically employs data encoding and decoding techniques, in which one or more extra bits are added to an original data stream during transmission and subsequently removed from the data stream to recover the original data. In the serial data transmission system, a clock synthesizer typically generates a clock signal having a stepped up frequency for use in increasing the transmission rate of the encoded data stream (i.e., the data stream including the extra bits). After the extra bits are removed to produce the decoded data stream, the clock synthesizer typically steps down the clock frequency to return to the original data transmission rate.
However, using a clock synthesizer to generate desired stepped up/stepped down clock frequencies in a serial data transmission system can be problematic. For example, the desired step up (step down) in frequency must be precisely performed to match the increase (decrease) of the data transmission rate after encoding (decoding) the data. For example, in the event the data encoding adds one extra bit for every 16 bits of the original data stream, the ratio of the original data transmission rate to the stepped up clock frequency must be 16/17. Alternatively, in the event the data encoding adds one extra bit for every 32 bits of the original data stream, the ratio of the original data transmission rate to the stepped-up frequency must be 32/33. The frequency difference between the clock signals employed with the original data stream and the encoded data stream can therefore be relatively small.
Conventional clock synthesizers capable of precise frequency generation typically employ a Phase Locked Loop (PLL). However, PLL-based clock synthesizers have drawbacks in that they are relatively costly and bulky and typically consume a significant amount of power. These drawbacks can preclude the implementation of PLL-based clock synthesizers within low-cost low-power Integrated Circuits (ICs).
Alternative clock synthesizer configurations may include a counter capable of counting to N to generate a first clock frequency and effectively blanking out the Nth pulse to generate a reduced clock frequency. However, such clock synthesizer configurations employing counters also have drawbacks in that they are typically only used for providing a step down in frequency and are generally not used in applications that require both stepped up and stepped down clock frequencies.
It would therefore be desirable to have an improved clock synthesizer that provides a desired step up/step down in clock frequency and avoids the drawbacks of conventional clock synthesizers.